Ventura Engineering Environment

PDK Management & Toolchain Documentation (Version 2026.1)

1. Global Environment Initialization

Before starting any work, ensure your session is clean. Use ml (Lmod) to manage software versions.

# 1. Clear old environment variables
ml purge

# 2. Load the PDK (Automatically loads Virtuoso/Spectre)
ml tsmc65

# 3. Setup local project files (First time only)
setup_project

Available PDKs

  • TSMC 65nm / 90nm
  • NCSU FreePDK45
  • GPDK 45nm
  • SkyWater 130nm

License Servers

  • Cadence: 5280@volta
  • Synopsys: 27000@volta
  • Siemens: 1717@volta

Default Tier

Virtuoso Studio GXL is the default suite for all Ventura users to ensure full feature access.

Cadence Design Systems (Custom IC)

Use for Analog/Mixed-Signal design, Schematic Entry, and Layout.

# Start Virtuoso in background
virtuoso &
Pro-Tip: If schematic labels or layout colors are missing, type drLoadDrf(getShellEnvVar("PDK_DISPLAY_DRF")) in the Virtuoso Command Interpreter Window (CIW).

Synopsys (Digital Synthesis)

Use for Logic Synthesis (Design Compiler) and Digital Implementation (Innovus/ICC2).

# Start Design Compiler (Shell Mode)
dc_shell -f scripts/synthesis.tcl

# Start Design Vision (GUI Mode)
design_vision &

Siemens EDA (Physical Verification)

Use Calibre for Sign-off DRC, LVS, and Parasitic Extraction (PEX).

# Check Rule File Paths
echo $MGC_CALIBRE_DRC_RULES_FILE
echo $MGC_CALIBRE_LVS_RULES_FILE

9. Common Troubleshooting

Issue Terminal Command Explanation
"Cell is Locked" cls Deletes *.cdslck files preventing editing.
Frozen GUI cdsPerfDiag -p [PID] Opens the Health Monitor for the frozen process.
Library Redefinition UNDEFINE basic Add to cds.lib to fix "basic redefines" warning.
Missing Bindkeys load("bindkeys.il") Run in CIW if 'W' or 'R' keys stop working.